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| TC55VCM208ASTN40,55 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 524,288-WORD BY 8-BIT FULL CMOS STATIC RAM DESCRIPTION The TC55VCM208ASTN is a 4,194,304-bit static random access memory (SRAM) organized as 524,288 words by 8 bits. Fabricated using Toshiba's CMOS Silicon gate process technology, this device operates from a single 2.3 to 3.6 V power supply. Advanced circuit technology provides both high speed and low power at an operating current of 3 mA/MHz and a minimum cycle time of 40 ns. It is automatically placed in low-power mode at 0.7 A standby current (at VDD = 3 V, Ta = 25C, typical) when chip enable ( CE1 ) is asserted high or (CE2) is asserted low. There are three control inputs. CE1 and CE2 are used to select the device and for data retention control, and output enable ( OE ) provides fast memory access. This device is well suited to various microprocessor system applications where high speed, low power and battery backup are required. And, with a guaranteed operating extreme temperature range of -40 to 85C, the TC55VCM208ASTN can be used in environments exhibiting extreme temperature conditions. The TC55VCM208ASTN is available in a plastic 40-pin thin-small outline package (TSOP). FEATURES * * * * * * * Low-power dissipation Operating: 9 mW/MHz (typical) Single power supply voltage of 2.3 to 3.6 V Power down features using CE1 and CE2 Data retention supply voltage of 1.5 to 3.6 V Direct TTL compatibility for all inputs and outputs Wide operating temperature range of -40 to 85C Standby Current (maximum): 3.6 V 3.0 V 10 A 5 A * Access Times: TC55VCM208ASTN 40 Access Time CE1 Access Time CE2 OE Access Time Access Time 40 ns 40 ns 40 ns 25 ns 55 55 ns 55 ns 55 ns 30 ns * Package: TSOP 40-P-1014-0.50 (Weight:0.30 g typ) PIN ASSIGNMENT (TOP VIEW) 40 PIN TSOP PIN NAMES A0~A18 Address Inputs 1 40 CE1 , CE2 R/W OE LB , UB Chip Enable Read/Write Control Output Enable Data Byte Control Data Inputs/Outputs Power Ground No Connection Option 20 (Normal) 21 I/O1~I/O16 VDD GND NC OP* *: OP pin must be open or connected to GND. Pin No. Pin Name Pin No. Pin Name 1 A16 21 A0 2 A15 22 CE1 3 A14 23 GND 4 A13 24 OE 5 A12 25 I/O1 6 A11 26 I/O2 7 A9 27 I/O3 8 A8 28 I/O4 9 R/W 29 NC 10 CE2 30 VDD 11 OP 31 VDD 12 NC 32 I/O5 13 A18 33 I/O6 14 A7 34 I/O7 15 A6 35 I/O8 16 A5 36 A10 17 A4 37 NC 18 A3 38 NC 19 A2 39 GND 20 A1 40 A17 2003-08-11 1/12 TC55VCM208ASTN40,55 BLOCK DIAGRAM CE A6 A7 A8 A9 A11 A12 A13 A14 A15 A16 A18 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 VDD ROW ADDRESS BUFFER ROW ADDRESS REGISTER ROW ADDRESS DECODER GND MEMORY CELL ARRAY 2,048 x 256 x 8 (4,194,304) SENSE AMP DATA CONTROL COLUMN ADDRESS DECODER CLOCK GENERATOR COLUMN ADDERSS REGISTER COLUMN ADDRESS BUFFER CE A0 A1 A2 A3 A4 A5 A10 A17 OE R/W CE1 CE2 CE OPERATING MODE MODE Read Write Output Deselect Standby * = don't care H = logic high L = logic low CE1 L L L H * CE2 H H H * OE L * R/W H L H * * I/O1~I/O8 Output Input High-Z High-Z High-Z POWER IDDO IDDO IDDO IDDS IDDS H * * L MAXIMUM RATINGS SYMBOL VDD VIN VI/O PD Tsolder Tstg Topr Power Supply Voltage Input Voltage Input/Output Voltage Power Dissipation Soldering Temperature (10s) Storage Temperature Operating Temperature RATING VALUE -0.3~4.2 -0.3*~4.2 -0.5~VDD + 0.5 UNIT V V V W C C C 0.6 260 -55~150 -40~85 *: -2.0 V when measured at a pulse width of 20ns 2003-08-11 2/12 TC55VCM208ASTN40,55 DC RECOMMENDED OPERATING CONDITIONS (Ta = -40 to 85C) SYMBOL VDD VIH VIL VDH PARAMETER Power Supply Voltage Input High Voltage Input Low Voltage Data Retention Supply Voltage VDD = 2.3 V~2.7 V VDD = 2.7 V~3.6 V MIN 2.3 2.0 2.2 -0.3* TYP MAX 3.6 VDD + 0.3 VDD x 0.24 3.6 UNIT V V V V 1.5 *: -2.0 V when measured at a pulse width of 20ns DC CHARACTERISTICS (Ta = -40 to 85C, VDD = 2.3 to 3.6 V) SYMBOL IIL IOH IOL ILO PARAMETER Input Leakage Current VIN = 0 V~VDD TEST CONDITION MIN -0.5 TYP MAX UNIT 1.0 1.0 A Output High Current VOH = VDD - 0.5 V Output Low Current Output Leakage Current VOL = 0.4 V CE1 = VIH or CE2 = VIL or R/W = VIL or OE = VIH, VOUT = 0 V~VDD CE1 = VIL and CE2 = VIH and R/W = VIH, IOUT = 0 mA, Other Input = VIH/VIL Operating Current CE1 = 0.2 V and CE2 = VDD - 0.2 V and R/W = VDD - 0.2 V, IOUT = 0 mA, Other Input = VDD - 0.2 V/0.2 V CE1 = VIH or CE2 = VIL VDD = Ta = -40~85C 3.3V 0.3 V Standby Current tcycle MIN 1 s MIN mA mA A 2.1 35 mA 8 30 mA IDDO1 IDDO2 1 s 3 1 10 A IDDS1 mA IDDS2 CE1 = VDD - 0.2 V or CE2 = 0.2 V Ta = 25C VDD =3.0 V Ta = -40~40C Ta = -40~85C 0.7 2 5 CAPACITANCE (Ta = 25C, f = 1 MHz) SYMBOL CIN COUT Note: PARAMETER Input Capacitance Output Capacitance VIN = GND VOUT = GND TEST CONDITION MAX 10 10 UNIT pF pF This parameter is periodically sampled and is not 100% tested. 2003-08-11 3/12 TC55VCM208ASTN40,55 AC CHARACTERISTICS AND OPERATING CONDITIONS (Ta = -40 to 85C, VDD = 2.7 to 3.6 V) READ CYCLE TC55VCM208ASTN SYMBOL PARAMETER MIN tRC tACC tCO1 tCO2 tOE tCOE tOEE tOD tODO tOH Read Cycle Time Address Access Time Chip Enable( CE1 ) Access Time Chip Enable(CE2) Access Time Output Enable Access Time Chip Enable Low to Output Active Output Enable Low to Output Active Chip Enable High to Output High-Z Output Enable High to Output High-Z Output Data Hold Time 40 40 MAX 55 MIN 55 UNIT MAX 40 40 40 25 55 55 55 30 ns 5 0 5 0 20 20 25 25 10 10 WRITE CYCLE TC55VCM208ASTN SYMBOL PARAMETER MIN tWC tWP tCW tAS tWR tODW tOEW tDS tDH Note: Write Cycle Time Write Pulse Width Chip Enable to End of Write Address Setup Time Write Recovery Time R/W Low to Output High-Z R/W High to Output Active Data Setup Time Data Hold Time 40 30 35 0 0 40 MAX 55 MIN 55 40 45 0 0 UNIT MAX ns 20 25 0 20 0 0 25 0 tOD, tODO and tODW are specified in time when an output becomes high impedance, and are not judged depending on an output voltage level. 2003-08-11 4/12 TC55VCM208ASTN40,55 AC CHARACTERISTICS AND OPERATING CONDITIONS (Ta = -40 to 85C, VDD = 2.3 to 3.6 V) READ CYCLE TC55VCM208ASTN SYMBOL PARAMETER MIN tRC tACC tCO1 tCO2 tOE tCOE tOEE tOD tODO tOH Read Cycle Time Address Access Time Chip Enable( CE1 ) Access Time Chip Enable(CE2) Access Time Output Enable Access Time Chip Enable Low to Output Active Output Enable Low to Output Active Chip Enable High to Output High-Z Output Enable High to Output High-Z Output Data Hold Time 55 40 MAX 55 MIN 70 UNIT MAX 55 55 55 30 70 70 70 35 ns 5 0 5 0 25 25 30 30 10 10 WRITE CYCLE TC55VCM208ASTN SYMBOL PARAMETER MIN tWC tWP tCW tAS tWR tODW tOEW tDS tDH Note: Write Cycle Time Write Pulse Width Chip Enable to End of Write Address Setup Time Write Recovery Time R/W Low to Output High-Z R/W High to Output Active Data Setup Time Data Hold Time 55 40 45 0 0 40 MAX 55 MIN 70 50 55 0 0 UNIT MAX ns 25 30 0 25 0 0 30 0 tOD, tODO and tODW are specified in time when an output becomes high impedance, and are not judged depending on an output voltage level. 2003-08-11 5/12 TC55VCM208ASTN40,55 AC TEST CONDITIONS PARAMETER Input pulse level tR, tF Timing measurements Reference level Output load TEST CONDITION 0.2 V, VDD x 0.7 V + 0.2 V 1V / ns(Fig.1) VDD x 0.5 VDD x 0.5 30 pF + 1 TTL Gate(Fig.2) Fig.1 : Input rise and fall time Fig.2 : Output load VTM VDD Typ GND 10% 1 V/ns tR 90% 90% 10% 1 V/ns tF R1 Dout R1 = 810 R2 = 1610 VTM = 2.3 V R2 30 pF 2003-08-11 6/12 TC55VCM208ASTN40,55 TIMING DIAGRAMS READ CYCLE (See Note 1) tRC Address A0~A18 tACC tCO1 CE1 tCO2 CE2 tOE OE tOEE DOUT I/O1~8 Hi-Z tCOE INDETERMINATE tODO VALID DATA OUT Hi-Z tOD tOH WRITE CYCLE 1 (R/W CONTROLLED) (See Note 4) tWC Address A0~A18 tAS R/W tCW CE1 tCW CE2 tODW DOUT I/O1~8 (See Note 2) Hi-Z tDS DIN I/O1~8 (See Note 5) tDH (See Note 5) tOEW (See Note 3) tWP tWR VALID DATA IN 2003-08-11 7/12 TC55VCM208ASTN40,55 WRITE CYCLE 2 ( CE1 CONTROLLED) (See Note 4) tWC Address A0~A18 tAS R/W tCW CE1 tCW CE2 tCOE DOUT I/O1~8 Hi-Z tDS DIN I/O1~8 (See Note 5) tDH tODW Hi-Z tWP tWR VALID DATA IN WRITE CYCLE 3 (CE2 CONTROLLED) (See Note 4) tWC Address A0~A18 tAS R/W tCW CE1 tCW CE2 tCOE DOUT I/O1~8 Hi-Z tDS DIN I/O1~8 (See Note 5) tDH tODW Hi-Z tWP tWR VALID DATA IN 2003-08-11 8/12 TC55VCM208ASTN40,55 Note: (1) (2) (3) (4) (5) R/W remains HIGH for the read cycle. If CE1 goes LOW(or CE2 goes HIGH) coincident with or after R/W goes LOW, the outputs will remain at high impedance. If CE1 goes HIGH(or CE2 goes LOW) coincident with or before R/W goes HIGH, the outputs will remain at high impedance. If OE is HIGH during the write cycle, the outputs will remain at high impedance. Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be applied. DATA RETENTION CHARACTERISTICS (Ta = -40 to 85C) SYMBOL VDH PARAMETER Data Retention Supply Voltage VDH = 3.6 V Ta = -40~85C IDDS2 Standby Current VDH = 3.0 V Ta = -40~40C Ta = -40~85C MIN 1.5 TYP MAX 3.6 10 2 5 UNIT V A tCDR tR Chip Deselect to Data Retention Mode Time Recovery Time 0 5 ns ms CE1 CONTROLLED DATA RETENTION MODE VDD (See Note 1) VDD 2.3 V DATA RETENTION MODE (See Note 2) VIH tCDR CE1 GND VDD - 0.2 V (See Note 2) tR CE2 CONTROLLED DATA RETENTION MODE VDD (See Note 3) VDD 2.3 V DATA RETENTION MODE CE2 VIH VIL GND tCDR 0.2 V tR 2003-08-11 9/12 TC55VCM208ASTN40,55 Note: (1) (2) (3) In CE1 controlled data retention mode, minimum standby current mode is entered when CE2 0.2 V or CE2 VDD - 0.2 V. When CE1 is operating at the VIH(min.) level, the operating current is given by IDDS1 during the transition of VDD from 2.3(2.7) to 2.2V(2.4 V). In CE2 controlled data retention mode, minimum standby current mode is entered when CE2 0.2 V. 2003-08-11 10/12 TC55VCM208ASTN40,55 PACKAGE DIMENSIONS Weight:0.30 g (typ) 2003-08-11 11/12 TC55VCM208ASTN40,55 RESTRICTIONS ON PRODUCT USE * The information contained herein is subject to change without notice. 030619EBA * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. * TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. * The products described in this document are subject to the foreign exchange and foreign trade laws. * TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced and sold, under any law and regulations. 2003-08-11 12/12 |
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